The quest to develop larger and larger semiconductors of the dynamic random access memory (DRAM) type is a well-known goal. The industry has steadily progressed from DRAMs of the 16K type, shown in U.S. Pat. No. 4,081,701 issued to White, McAdams and Redwine, and the 64K type, shown in U.S. Pat. No. 4,055,444 issued to Rao, to DRAMs of the 1M type, as described in U.S. Pat. No. 4,658,377 issued to McElroy. DRAMs of the 4M type are now being produced. Production plans for 16M DRAMs of submicron technology now exist and experimentation of 64M DRAMs has begun. One factor furthering the development of larger DRAMs is the reduction in memory cell geometries as illustrated in U.S. Pat. No. 4,240,092 to Kuo (a planar capacitor cell), and as illustrated in U.S. Pat. No. 4,721,987 to Baglee et al. (a trench capacitor cell). In a trench capacitor cell device, the capacitance of the device is increased by etching a groove, or trench, in the capacitance region. The trench capacitor cell of Baglee describes its upper plate as a polysilicon layer extending into the trench. This polysilicon layer extends over the face of the silicon bar to form field plate isolation over the face of the bar.
In developing DRAMs of the trench capacitor type, process engineers have observed a problem near the top of the trench they describe as "Gated Diode Leakage". This problem manifest itself through a leakage current. Current may flow through the upper portion of the storage node on the top of the trench wall edge into the silicon substrate by a band to band tunneling effect, thereby reducing the charge placed upon the storage node.
It is the object of this invention to provide a method to eliminate undesirable gated diode leakage near the top of the trench for trench capacitor type devices such as high density dynamic random access memories.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification, together with the drawings.